Estimation of Circuit Activity Considering Signal Corelations and Simultaneous Switching
نویسندگان
چکیده
This paper presents accurate estimation of signal activity at the internal nodes of CMOS combinational logic circuits. The methodology is based on stochastic model of logic signals and takes correlations and simultaneous switching of signals at logic gate inputs into consideration. In combinational logic synthesis, in order to minimize spurious transitions due to nite propagation delays, it is crucial to balance all signal paths and to reduce the logic depth [4]. As a result of balancing delays through di erent paths, the inputs to logic gates may switch at approximately the same time. We have developed and implemented an technique to calculate signal probability and switching activity of the CMOS combinational logic circuits. Experimental results show that if simultaneous switching is not considered the switching activities of the internal nodes can be o by more than 100% compared to simulation based techniques. In contrast, our technique is on the average within 2% of logic simulation results.
منابع مشابه
Test Power Reduction by Simultaneous Don’t Care Filling and Ordering of Test Patterns Considering Pattern Dependency
Estimating and minimizing the maximum power dissipation during testing is an important task in VLSI circuit realization since the power value affects the reliability of the circuits. Therefore during testing a methodology should be adopted to minimize power consumption. Test patterns generated with –D 1 option of ATALANTA contains don’t care bits (x bits). By suitable filling of don’t cares can...
متن کاملEstimation of On-Chip Simultaneous Switching Noise on Signal Delay in Synchronous CMOS Integrated Circuits
On-chip parasitic inductance inherent to the power distribution network has becoming significant in high speed digital circuits. Therefore, current surges result in voltage fluctuations within the power distribution network, creating delay uncertainty. On-chip simultaneous switching noise should therefore be considered when estimating the propagation delay of a CMOS logic gate in high speed syn...
متن کاملModeling and Simulation of Substrate Noise in Mixed-Signal Circuits Applied to a Special VCO
The mixed-signal circuits with both analog and digital blocks on a single chip have wide applications in communication and RF circuits. Integrating these two blocks can cause serious problems especially in applications requiring fast digital circuits and high performance analog blocks. Fast switching in digital blocks generates a noise which can be introduced to analog circuits by the common su...
متن کاملDelay Uncertainty Due to On-chip Simultaneous Switching Noise in High Performance Cmos Integrated Circuits
On-chip parasitic inductance inherent to the power supply rails has become significant in high speed digital circuits. Therefore, current surges result in voltage fluctuations within the power distribution networks, creating delay uncertainty. On-chip simultaneous switching noise should therefore be considered when estimating the propagation delay of a CMOS logic gate in high speed synchronous ...
متن کاملA Novel Sampling Approach in GNSS-RO Receivers with Open Loop Tracking Method
Propagation of radio occultation (RO) signals through the lower troposphere results in high phase acceleration and low signal to noise ratio signal. The excess Doppler estimation accuracy in lower troposphere is very important in receiving RO signals which can be estimated by sliding window spectral analysis. To do this, various frequency estimation methods such as MUSIC and ESPRIT can be adopt...
متن کامل